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TheEmbeddedRust/usb-avr-lib:main TheEmbeddedRust/usb-avr-lib:test
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compare: TheEmbeddedRust/usb-avr-lib:12104cdc0bed3bd7c0eb6226bfcb6c9edbdd3445
TheEmbeddedRust/usb-avr-lib:test TheEmbeddedRust/usb-avr-lib:main
1 Commits
test .. 12104cdc0b
Author SHA1 Message Date
doryan 12104cdc0b feat: remove proc-macro dependency 2025-04-24 21:36:02 +03:00
4 changed files with 160 additions and 161 deletions
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Cargo.toml
+2 -4
View File
@@ -1,5 +1,5 @@
[package]
name = "usb-avr"
name = "usb_avr"
version = "0.1.0"
edition = "2021"
@@ -11,11 +11,9 @@ embedded-hal = "1.0"
usb-device = "0.3.2"
[dependencies.avr-device]
version = "0.8.1"
version = "0.5.4"
features = ["atmega32u4"]
# The latest releases of `proc-macro2` do not support the rust toolchain that
# we use. Thus, we must fix this dependency to an older version where our
# toolchain is still supported. See https://github.com/Rahix/avr-hal/issues/537
# [build-dependencies.proc-macro2]
# version = "=1.0.79"
rust-toolchain.toml
+4
View File
@@ -0,0 +1,4 @@
[toolchain]
channel = "nightly-2024-06-13"
components = [ "rust-src" ]
profile = "complete"
src/lib.rs
+124 -114
View File
@@ -6,7 +6,7 @@ use avr_device::{asm::delay_cycles, interrupt::free};
use usb_device::{
bus::{PollResult, UsbBus},
endpoint::{EndpointAddress, EndpointType},
Result as UsbResult, UsbDirection as Dir, UsbError,
Result as UsbResult, UsbDirection, UsbError,
};
mod types;
@@ -14,24 +14,25 @@ pub use types::*;
use types::{DPRAM_SIZE, ENDPOINTS_ALLOC_LAYOUT, ONE_MS_16_MGHZ};
const RESTRICT_RW_FLAG: u8 = !(1 << 5);
const USBINT_CLEAR: u8 = 1 << 0;
const UDINT_CLEAR: u8 = !(1 << 7 | 1 << 1);
impl<const L: usize> UsbBus for UsbDevice<L> {
fn alloc_ep(
&mut self,
ep_dir: Dir,
ep_dir: UsbDirection,
ep_addr: Option<EndpointAddress>,
ep_type: EndpointType,
max_packet_size: u16,
_interval: u8,
) -> UsbResult<EndpointAddress> {
let target_ep_index = match ep_addr {
Some(ep) if ep.index() == 0 && ep_dir == Dir::In => {
return ep_addr.ok_or(UsbError::InvalidState);
} // TODO: rewrite to bind pattern with @
Some(ep) if !self.ep_table[ep.index()].is_allocated => Ok(ep),
// Handle first endpoint. //
free(|_cs| {
if ep_addr == Some(EndpointAddress::from_parts(0, UsbDirection::In)) {
Ok(ep_addr.unwrap())
} else {
let address = match ep_addr {
// If current endpoint doesn't allocated, assign ep_addr to variable. //
Some(addr) if !self.ep_table[addr.index()].is_allocated => addr,
// If ep_aadr not provided, or current endpoint is allocated, try to find next free endpoint, otherwise return UsbError. //
_ => {
let index = self
.ep_table
@@ -39,31 +40,44 @@ impl<const L: usize> UsbBus for UsbDevice<L> {
.enumerate()
.skip(1)
.find(|(index, ep)| {
!ep.is_allocated && max_packet_size <= ENDPOINTS_ALLOC_LAYOUT[*index]
!ep.is_allocated
&& max_packet_size <= ENDPOINTS_ALLOC_LAYOUT[*index]
})
.map(|(index, _)| index)
.ok_or(UsbError::EndpointOverflow)?;
.ok_or(UsbError::EndpointOverflow)?
.0;
Ok(EndpointAddress::from_parts(index, ep_dir))
EndpointAddress::from_parts(index, ep_dir)
}
}?;
};
// Select endpoint info by address index. //
let target_endpoint = &mut self.ep_table[address.index()];
// Get power of two number of endpoint size. //
let ep_size = max(8, max_packet_size.next_power_of_two());
// Endpoint allocation marker. //
if DPRAM_SIZE - self.dpram_already_used < ep_size {
return Err(UsbError::EndpointMemoryOverflow);
}
Err(UsbError::EndpointMemoryOverflow)
} else {
// Set endpoint parameters. //
let target_ep = &mut self.ep_table[target_ep_index.index()];
target_endpoint.set_dir(ep_dir);
target_endpoint.set_type(ep_type);
target_endpoint.set_size(ep_size)?;
target_ep.set_dir(ep_dir);
target_ep.set_type(ep_type);
target_ep.set_size(ep_size)?;
// Add used dpram memory. //
target_ep.is_allocated = true;
target_endpoint.is_allocated = true;
self.dpram_already_used += ep_size;
Ok(target_ep_index)
Ok(address)
}
}
})
}
fn enable(&mut self) {
@@ -72,71 +86,70 @@ impl<const L: usize> UsbBus for UsbDevice<L> {
// Enable USB pads regulators. //
usb.uhwcon().modify(|_, w| w.uvrege().set_bit());
usb.uhwcon.modify(|_, w| w.uvrege().set_bit());
// PLL configuration //
pll.pllcsr().write(|w| w.pindiv().set_bit());
pll.pllcsr.write(|w| w.pindiv().set_bit());
pll.pllfrq()
.write(|w| w.pdiv().mhz96().plltm().factor_1().pllusb().set_bit());
pll.pllfrq
.write(|w| w.pdiv().mhz96().plltm().factor_15().pllusb().set_bit());
// Enable PLL //
pll.pllcsr().modify(|_, w| w.plle().set_bit());
pll.pllcsr.modify(|_, w| w.plle().set_bit());
// Check PLL lock //
while pll.pllcsr().read().plock().bit_is_clear() {}
while pll.pllcsr.read().plock().bit_is_clear() {}
// Enable USB interface. //
usb.usbcon()
usb.usbcon
.modify(|_, w| w.usbe().set_bit().otgpade().set_bit());
// Unfreeze clock. //
usb.usbcon()
usb.usbcon
.modify(|_, w| w.frzclk().clear_bit().vbuste().set_bit());
// Endpoint configuration //
self.allocated_endpoints().for_each(|(i, _ep)| {
let _ = self.configure_endpoint(cs, i);
self.configure_endpoint(cs, i).unwrap();
});
// Set high speed and attach the USB. //
usb.udcon()
usb.udcon
.modify(|_, w| w.detach().clear_bit().lsm().clear_bit());
// Interrupts. //
usb.udien()
usb.udien
.modify(|_, w| w.eorste().set_bit().sofe().set_bit());
})
}
fn force_reset(&self) -> UsbResult<()> {
let set_detach = |bit| {
free(|cs| {
self.usb
.borrow(cs)
.udcon()
.modify(|_, w| w.detach().bit(bit));
let usbcon = &self.usb.borrow(cs).usbcon;
usbcon.modify(|_, w| w.usbe().set_bit());
});
};
set_detach(true);
delay_cycles(ONE_MS_16_MGHZ);
set_detach(false);
free(|cs| {
let usbcon = &self.usb.borrow(cs).usbcon;
usbcon.modify(|_, w| w.usbe().set_bit());
});
Ok(())
}
fn is_stalled(&self, ep_addr: EndpointAddress) -> bool {
free(|cs| match self.select_endpoint(cs, ep_addr.index()) {
Ok(_) => self.usb.borrow(cs).ueconx().read().stallrq().bit_is_set(),
Ok(_) => self.usb.borrow(cs).ueconx.read().stallrq().bit_is_set(),
Err(_) => false,
})
}
@@ -145,14 +158,12 @@ impl<const L: usize> UsbBus for UsbDevice<L> {
free(|cs| {
let usb = self.usb.borrow(cs);
let (udint, udien, usbint) =
(usb.udint().read(), usb.udien().read(), usb.usbint().read());
let (udint, udien, usbint) = (usb.udint.read(), usb.udien.read(), usb.usbint.read());
if usbint.vbusti().bit_is_set() {
usb.usbint()
.write(|w| unsafe { w.bits(USBINT_CLEAR) }.vbusti().clear_bit());
if usb.usbsta().read().vbus().bit_is_set() {
usb.usbint
.write(|w| unsafe { w.bits(0x01) }.vbusti().clear_bit());
if usb.usbsta.read().vbus().bit_is_set() {
return PollResult::Resume;
} else {
return PollResult::Suspend;
@@ -172,21 +183,20 @@ impl<const L: usize> UsbBus for UsbDevice<L> {
}
if udint.sofi().bit_is_set() {
usb.udint()
.write(|w| unsafe { w.bits(UDINT_CLEAR) }.sofi().clear_bit());
usb.udint
.write(|w| unsafe { w.bits(0x7d) }.sofi().clear_bit());
}
if usb.usbcon().read().frzclk().bit_is_clear() {
if usb.usbcon.read().frzclk().bit_is_clear() {
let (mut ep_out, mut ep_in_complete, mut ep_setup) = (0u16, 0u16, 0u16);
let pending_ins = self.pending_ins.borrow(cs);
for ep_index in 0usize..self.ep_table.len() {
if !self.ep_table[ep_index].is_allocated {
continue;
}
for (ep_index, _ep) in self.allocated_endpoints() {
if self.select_endpoint(cs, ep_index).is_err() {
break;
} else {
let ueintx = usb.ueintx.read();
if self.select_endpoint(cs, ep_index).is_ok() {
let ueintx = usb.ueintx().read();
if ueintx.rxouti().bit_is_set() {
ep_out |= 1 << ep_index;
}
@@ -200,7 +210,6 @@ impl<const L: usize> UsbBus for UsbDevice<L> {
}
}
}
if ep_out | ep_in_complete | ep_setup != 0 {
return PollResult::Data {
ep_out,
@@ -217,29 +226,29 @@ impl<const L: usize> UsbBus for UsbDevice<L> {
free(|cs| {
let usb = self.usb.borrow(cs);
self.select_endpoint(cs, ep_addr.index())?;
if let Err(error) = self.select_endpoint(cs, ep_addr.index()) {
Err(error)
} else {
let ep = &self.ep_table[ep_addr.index()];
if ep.ep_type == 0 {
let ueintx = usb.ueintx().read();
let ueintx = usb.ueintx.read();
if ueintx.rxouti().bit_is_clear() && ueintx.rxstpi().bit_is_clear() {
return Err(UsbError::WouldBlock);
}
let buf_size = self.get_size(cs);
if buf.len() < buf_size {
return Err(UsbError::BufferOverflow);
}
for byte in &mut buf[..buf_size] {
*byte = usb.uedatx().read().bits();
*byte = usb.uedatx.read().bits();
}
usb.ueintx().write(|w| {
unsafe { w.bits(RESTRICT_RW_FLAG) }
usb.ueintx.write(|w| {
unsafe { w.bits(0xdf) }
.rxouti()
.clear_bit()
.rxstpi()
@@ -248,32 +257,30 @@ impl<const L: usize> UsbBus for UsbDevice<L> {
Ok(buf_size)
} else {
if usb.ueintx().read().rxouti().bit_is_clear() {
if usb.ueintx.read().rxouti().bit_is_clear() {
return Err(UsbError::WouldBlock);
}
usb.ueintx()
.write(|w| unsafe { w.bits(RESTRICT_RW_FLAG) }.rxouti().clear_bit());
usb.ueintx
.write(|w| unsafe { w.bits(0xdf) }.rxouti().clear_bit());
let mut bytes_read = 0;
for slot in buf {
if usb.ueintx().read().rwal().bit_is_clear() {
if usb.ueintx.read().rwal().bit_is_clear() {
break;
}
*slot = usb.uedatx().read().bits();
*slot = usb.uedatx.read().bits();
bytes_read += 1;
}
if usb.ueintx().read().rwal().bit_is_set() {
if usb.ueintx.read().rwal().bit_is_set() {
return Err(UsbError::BufferOverflow);
}
usb.ueintx()
.write(|w| unsafe { w.bits(RESTRICT_RW_FLAG) }.fifocon().clear_bit());
usb.ueintx
.write(|w| unsafe { w.bits(0xdf) }.fifocon().clear_bit());
Ok(bytes_read)
}
}
})
}
@@ -281,23 +288,23 @@ impl<const L: usize> UsbBus for UsbDevice<L> {
free(|cs| {
let usb = self.usb.borrow(cs);
usb.udint().modify(|_, w| w.eorsti().clear_bit());
usb.udint.modify(|_, w| w.eorsti().clear_bit());
self.allocated_endpoints().for_each(|(i, _)| {
let _ = self.configure_endpoint(cs, i);
self.configure_endpoint(cs, i).unwrap();
});
// Clear resume informations. //
usb.udint().write(|w| {
unsafe { w.bits(UDINT_CLEAR) }
usb.udint.write(|w| {
unsafe { w.bits(0x7d) }
.wakeupi()
.clear_bit()
.suspi()
.clear_bit()
});
usb.udien()
usb.udien
.modify(|_, w| w.wakeupe().clear_bit().suspe().set_bit());
})
}
@@ -308,24 +315,24 @@ impl<const L: usize> UsbBus for UsbDevice<L> {
// PLL enable //
pll.pllcsr()
pll.pllcsr
.modify(|_, w| w.pindiv().set_bit().plle().set_bit());
while pll.pllcsr().read().plock().bit_is_clear() {}
while pll.pllcsr.read().plock().bit_is_clear() {}
// Resuming //
usb.usbcon().modify(|_, w| w.frzclk().clear_bit());
usb.usbcon.modify(|_, w| w.frzclk().clear_bit());
usb.udint().write(|w| {
unsafe { w.bits(UDINT_CLEAR) }
usb.udint.write(|w| {
unsafe { w.bits(0x7d) }
.wakeupi()
.clear_bit()
.suspi()
.clear_bit()
});
usb.udien()
usb.udien
.modify(|_, w| w.wakeupe().clear_bit().suspe().set_bit());
})
}
@@ -336,14 +343,14 @@ impl<const L: usize> UsbBus for UsbDevice<L> {
// Set address. //
usb.udaddr().modify(|_, w| w.uadd().set(addr));
usb.udaddr.modify(|_, w| w.uadd().bits(addr));
// Note: ADDEN and UADD shall not be written at the same time.
// (written in atmega32u4/16u4 docs)
// Enable. //
usb.udaddr().modify(|_, w| w.adden().set_bit());
usb.udaddr.modify(|_, w| w.adden().set_bit());
});
}
@@ -351,7 +358,7 @@ impl<const L: usize> UsbBus for UsbDevice<L> {
free(|cs| {
let usb = self.usb.borrow(cs);
if self.select_endpoint(cs, ep_addr.index()).is_ok() {
usb.ueconx()
usb.ueconx
.modify(|_, w| w.stallrq().bit(stalled).stallrqc().bit(!stalled));
}
});
@@ -361,8 +368,8 @@ impl<const L: usize> UsbBus for UsbDevice<L> {
free(|cs| {
let (usb, pll) = (self.usb.borrow(cs), self.pll.borrow(cs));
usb.udint().write(|w| {
unsafe { w.bits(UDINT_CLEAR) }
usb.udint.write(|w| {
unsafe { w.bits(0x7d) }
.wakeupi()
.clear_bit()
.suspi()
@@ -371,49 +378,51 @@ impl<const L: usize> UsbBus for UsbDevice<L> {
// Suspend. //
usb.udien()
usb.udien
.modify(|_, w| w.wakeupe().set_bit().suspe().clear_bit());
// Freeze clock. //
usb.usbcon().modify(|_, w| w.frzclk().set_bit());
usb.usbcon.modify(|_, w| w.frzclk().set_bit());
// Disable PLL. //
pll.pllcsr().modify(|_, w| w.plle().clear_bit());
pll.pllcsr.modify(|_, w| w.plle().clear_bit());
})
}
fn write(&self, ep_addr: EndpointAddress, buf: &[u8]) -> UsbResult<usize> {
free(|cs| {
let (usb, pending_ins) = (self.usb.borrow(cs), self.pending_ins.borrow(cs));
self.select_endpoint(cs, ep_addr.index())?;
let usb = self.usb.borrow(cs);
if let Err(error) = self.select_endpoint(cs, ep_addr.index()) {
Err(error)
} else {
let ep = &self.ep_table[ep_addr.index()];
// Endpoint type confitions //
if usb.ueintx().read().txini().bit_is_clear() {
if ep.ep_type == 0 {
if usb.ueintx.read().txini().bit_is_clear() {
return Err(UsbError::WouldBlock);
}
match ep.ep_type {
0 => {
if buf.len() > ep.get_size() {
return Err(UsbError::BufferOverflow);
}
for &byte in buf {
usb.uedatx().write(|w| w.set(byte));
usb.uedatx.write(|w| w.bits(byte));
}
usb.ueintx()
.write(|w| unsafe { w.bits(RESTRICT_RW_FLAG) }.txini().clear_bit());
usb.ueintx
.write(|w| unsafe { w.bits(0xdf) }.txini().clear_bit());
} else {
if usb.ueintx.read().txini().bit_is_clear() {
return Err(UsbError::WouldBlock);
}
_ => {
usb.ueintx().write(|w| {
unsafe { w.bits(RESTRICT_RW_FLAG) }
usb.ueintx.write(|w| {
unsafe { w.bits(0xdf) }
.txini()
.clear_bit()
.rxouti()
@@ -421,26 +430,27 @@ impl<const L: usize> UsbBus for UsbDevice<L> {
});
for &byte in buf {
if usb.ueintx().read().rwal().bit_is_set() {
usb.uedatx().write(|w| w.set(byte));
if usb.ueintx.read().rwal().bit_is_set() {
usb.uedatx.write(|w| w.bits(byte));
} else {
return Err(UsbError::BufferOverflow);
}
}
usb.ueintx().write(|w| {
unsafe { w.bits(RESTRICT_RW_FLAG) }
usb.ueintx.write(|w| {
unsafe { w.bits(0xdf) }
.rxouti()
.clear_bit()
.fifocon()
.clear_bit()
});
}
};
let pending_ins = self.pending_ins.borrow(cs);
pending_ins.set(pending_ins.get() | 1 << ep_addr.index());
Ok(buf.len())
}
})
}
}
src/types/usb_device.rs
+30 -43
View File
@@ -2,13 +2,13 @@ use core::cell::Cell;
use avr_device::{
atmega32u4::{PLL, USB_DEVICE},
interrupt::{free, CriticalSection, Mutex},
interrupt::{CriticalSection, Mutex},
};
use usb_device::{bus::UsbBusAllocator, endpoint::EndpointType, UsbDirection, UsbError};
#[allow(unused)]
#[derive(Default, Copy, Clone)]
pub struct USBEndpoint {
pub(crate) struct USBEndpoint {
pub(crate) is_allocated: bool,
pub(crate) size: u8,
pub(crate) ep_type: u8,
@@ -71,8 +71,8 @@ impl USBEndpoint {
pub struct UsbDevice<const L: usize> {
pub(crate) pll: Mutex<PLL>,
pub(crate) usb: Mutex<USB_DEVICE>,
pub(crate) pending_ins: Mutex<Cell<u8>>,
pub(crate) ep_table: [USBEndpoint; L],
pub(crate) pending_ins: Mutex<Cell<u8>>,
pub(crate) dpram_already_used: u16,
}
@@ -80,31 +80,27 @@ pub(crate) const MAX_ENDPOINTS: usize = 7;
pub(crate) const DPRAM_SIZE: u16 = 832;
pub(crate) const ENDPOINTS_ALLOC_LAYOUT: [u16; MAX_ENDPOINTS] = [64, 256, 64, 64, 64, 64, 64];
pub(crate) const ONE_MS_16_MGHZ: u32 = 16000;
pub(crate) const ENDPOINT_EPNUM_MASK: u8 = 0x07;
impl<const L: usize> UsbDevice<L> {
#[inline]
pub(crate) fn get_size(&self, cs: CriticalSection<'_>) -> usize {
let usb = self.usb.borrow(cs);
(((usb.uebchx.read().bits() as u16) << 8) | (usb.uebclx.read().bits() as u16)).into()
}
#[inline]
pub fn new(pll: PLL, usb: USB_DEVICE) -> UsbBusAllocator<Self> {
UsbBusAllocator::new(Self {
pll: Mutex::new(pll),
usb: Mutex::new(usb),
pending_ins: Mutex::new(Cell::new(0)),
ep_table: [USBEndpoint::default(); L],
pending_ins: Mutex::new(Cell::new(0u8)),
dpram_already_used: 0,
})
}
#[inline(always)]
pub fn get_usb_device<'u>(&'u self, cs: CriticalSection<'u>) -> &'u USB_DEVICE {
self.usb.borrow(cs)
}
#[inline(always)]
pub fn get_pll<'u>(&'u self, cs: CriticalSection<'u>) -> &'u PLL {
self.pll.borrow(cs)
}
#[inline(always)]
#[inline]
pub(crate) fn allocated_endpoints(&self) -> impl Iterator<Item = (usize, &USBEndpoint)> {
self.ep_table
.iter()
@@ -117,22 +113,21 @@ impl<const L: usize> UsbDevice<L> {
cs: CriticalSection<'_>,
endpoint_index: usize,
) -> Result<(), UsbError> {
let usb = self.usb.borrow(cs);
let endpoint_index = endpoint_index as u8;
if endpoint_index >= 7 {
return Err(UsbError::InvalidEndpoint);
}
let usb = self.usb.borrow(cs);
if usb.usbcon().read().frzclk().bit_is_set() {
if usb.usbcon.read().frzclk().bit_is_set() {
return Err(UsbError::InvalidState);
}
let endpoint_index = (endpoint_index as u8) & ENDPOINT_EPNUM_MASK;
usb.uenum.write(|w| w.bits(endpoint_index));
usb.uenum().write(|w| unsafe { w.bits(endpoint_index) });
if usb.uenum().read().bits() & ENDPOINT_EPNUM_MASK != endpoint_index {
return Err(UsbError::InvalidState);
if usb.uenum.read().bits() & 7 /* 0b111 */ != endpoint_index {
return Err(UsbError::InvalidEndpoint);
}
Ok(())
@@ -144,27 +139,25 @@ impl<const L: usize> UsbDevice<L> {
endpoint_index: usize,
) -> Result<(), UsbError> {
let usb = self.usb.borrow(cs);
let current_endpoint = self.ep_table[endpoint_index];
self.select_endpoint(cs, endpoint_index)?;
let current_endpoint = &self.ep_table[endpoint_index];
usb.uecfg1x().modify(|_, w| w.alloc().clear_bit());
match self.select_endpoint(cs, endpoint_index) {
Ok(_) => {
// Enable endpoint. //
usb.ueconx().modify(|_, w| w.epen().set_bit());
usb.ueconx.modify(|_, w| w.epen().set_bit());
usb.uecfg1x.modify(|_, w| w.alloc().clear_bit());
// Set markered endpoint parameters to uecfg0x/1x register. //
usb.uecfg0x().write(|w| unsafe {
usb.uecfg0x.modify(|_, w| {
w.epdir()
.bit(current_endpoint.ep_dir)
.eptype()
.bits(current_endpoint.ep_type)
});
usb.uecfg1x().write(|w| unsafe {
usb.uecfg1x.modify(|_, w| {
w.epbk()
.bits(0)
.epsize()
@@ -173,22 +166,16 @@ impl<const L: usize> UsbDevice<L> {
.set_bit()
});
usb.uecfg1x().modify(|_, w| w.alloc().set_bit());
if usb.uesta0x().read().cfgok().bit_is_clear() {
if usb.uesta0x.read().cfgok().bit_is_clear() {
Err(UsbError::EndpointMemoryOverflow)
} else {
usb.ueienx()
usb.ueienx
.modify(|_, w| w.rxoute().set_bit().rxstpe().set_bit());
Ok(())
}
}
#[inline(always)]
pub(crate) fn get_size(&self, cs: CriticalSection<'_>) -> usize {
let usb = self.usb.borrow(cs);
(((usb.uebchx().read().bits() as u16) << 8) | (usb.uebclx().read().bits() as u16)).into()
Err(exception) => Err(exception),
}
}
}